1. Field of the Invention
This invention relates to a power-consumption calculation method and apparatus. More particularly, the invention relates to a power-consumption calculation method and apparatus for calculating a predicted value of power consumed by a semiconductor device to be designed.
2. Description of the Related Art
Semiconductor devices such as system LSI chips bear circuits of ever greater scale. In order to design them, use is made of a top-down design technique for implementation from a high level of abstraction to a low level of abstraction. Broadly speaking, the top-down technique has three design stages, namely a behavioral level, RT (Register Transfer) level and gate level. Ordinarily, in the designing of a semiconductor device, verification of operation, verification of processing capability and verification of power consumption, etc., are performed by simulation. In particular, there is a tendency for a semiconductor device mounted on a portable device to be required to have a high performance with little consumption of power, and verification of consumed power at the design stage is of growing importance.
FIG. 8 illustrates a procedure for estimating power consumption by conducting a simulation at the gate level. Such estimation of power consumption at the gate level is as described in the specification of Japanese Patent Application Laid-Open No. 2001-265847 (Patent Document 1). In the designing of a system LSI chip or the like, an algorithm description 21 in which the functions of the semiconductor device (macro blocks) to be designed are described is converted to a hardware description (RTL description) 23 at the RT level by a behavioral synthesis unit 22. The RTL language 23 is converted to hardware language (gate-level netlist) 25 at the gate level by a logic synthesis unit 24.
Predicted values of power consumption of hardware (gates) such as multiplexers and registers are registered in a gate-power library 26 on a per-technology basis. On the basis of the gate-level list 25 input thereto, a power calculation unit 27 acquires power values, which conform to the operating states of each of the gates, from the gate-power library 26 while conducting a simulation at the gate level.
With estimation of power consumption at the gate level, the accuracy of estimation of power consumption of the semiconductor device to be designed can be improved by increasing the accuracy of the predicted value of power consumption of each gate registered in the gate-power library 26. However, simulation at the gate level takes time and using such estimation method of power consumption at the gate level in the designing of a semiconductor device, particularly one having circuitry of large scale, is unrealistic.
Power-consumption estimation in which a simulation is conducted at the RT level is available as a technique for shortening the time needed to estimate power consumption. FIG. 9 illustrates a procedure for estimation of power consumption in which a simulation is performed at the RT level. In the case of such power consumption at the RT level, the RTL description 23 obtained by behavioral synthesis is co-simulated by an RTL co-simulation unit 28. In the simulation, operating ratios that indicate the toggle rates or toggle transition probabilities of those gate circuits, which are to construct the semiconductor device, corresponding to storage elements such as registers and memories specified by the RTL description 23 are calculated.
The gate-level netlist 25 obtained by logic synthesis of the RTL description 23 and an operating ratio 29 of the storage element calculated by the RTL co-simulation unit 28 are input to an operating-ratio setting unit 30, which sets the operating ratio to each gate included in the gate-level netlist 25. With regard to those gates that correspond to the storage elements, the RTL description 23 and gate-level netlist are in one-to-one correspondence, and therefore the operating-ratio setting unit 30 sets the operating ratio of a gate corresponding to a storage element using, as is, the operating ratio 29 of the storage element that has entered from the RTL co-simulation unit 28.
With regard to gates other than those corresponding to storage elements, the RTL description 23 and gate-level netlist are not in one-to-one correspondence. Consequently, the operating ratio of the gate of a storage element cannot be input from the RTL co-simulation unit 28. However, since a gate other than one corresponding to a storage element is usually bracketed by storage elements or input pins, the operating ratio of this portion can be estimated from the operating ratio 29 of the storage element. Accordingly, the operating-ratio setting unit 30 causes the operating ratio 29 of the storage element or the operating ratio from the input pin to propagate through the netlist and sets the operating ratio of a gate other than a storage element. A power calculation unit 32 estimates the consumed power of each gate statically using an operating-ratio file 31, which is output from the operating-ratio setting unit 30 and in which an operating ratio has been set for every gate, and the gate-power library 26, thereby estimating the overall power consumption of the semiconductor device to be designed.
In estimation of power consumption at the RT level, the power calculation unit 32 estimates power consumption without conducting a simulation at the gate level. Since the level at which the simulation is performed is thus the RT level, which has a higher level of abstraction than the gate level, the estimation of power consumption at the RT level takes less time than the estimation of power consumption at the gate level illustrated in FIG. 8. However, in a case where the scale of the circuitry of the semiconductor device is large, a sufficiently high speed cannot be obtained even with estimation of power consumption at the RT level. This means that there is a need to perform the estimation of power consumption at still higher speed.
The art described in ORINOCO “Behavioral Level Low Power Estimation” <http://www.chipvision.com/> (Non-Patent Document 1) is an example of a technique that makes it possible to estimate power consumption at higher speed. FIG. 10 is a flowchart indicating the manner of estimation of power consumption described in Non-Patent Document 1. According to this technique, a routine for calculating operating ratio is inserted into an algorithm description (A) 41 described at the behavioral level (step S101), an algorithm description (B) 42 is obtained and this is simulated (step S102). This is a data structure generated by behavioral synthesis from the algorithm (B) 42. A CDFG (Control Data Flow Graph), which is produced by processing (scheduling) that converts the description of the algorithm to a cycle operation, is generated (step S103).
An operating-ratio file 43, which is obtained by the simulation at step S102, is assigned to the CDFG (step S104) generated at step S103, constraints such as number of resources and timing are set and processing that corresponds to binding processing implemented by operation synthesis is executed (step S105). According to Non-Patent Document 1, power consumption of the device to be designed is estimated at a level higher than the RT level based upon the environment thus constructed (step S106).
According to power-consumption estimation shown in FIG. 10 in which a simulation is conducted at a level higher than the RT level, the operating ratio is calculated by performing the simulation at the behavioral level, and the operating ratio is utilized to estimate power consumption in an environment constructed by generation of the CDFG and binding processing. In this case, estimation of power consumption can be speeded up but the algorithm description is an untimed description in which time has not been set. A problem which arises, therefore, is that the accuracy of the estimation of power consumption is low in comparison with a case where a hardware model is simulated dynamically. Further, there is no assurance that the environment constructed by CDFG generation and binding processing will correspond to the RTL description obtained later by behavioral synthesis of the algorithm description. A problem which arises, therefore, is that there is no assurance that the power consumption of a semiconductor device to be designed will be estimated correctly.
The specification of Japanese Patent Application Laid-Open No. 2001-109788 (Patent Document 2) describes a technique whereby a simulation of a semiconductor device to be designed can be performed at high speed. This reference proposes the clock level as a level whose degree of abstraction is lower than that of the operating level and higher than that of the RT level. The clock-level description differs from the RTL description, which is a structural description, in that it is a cycle-based description; it is a hardware model that operates at the same timing as that of the RTL description. According to Patent Document 2, a simulation is conducted using such a clock-level description. If the clock-level description and RTL description are compared with regard to the same hardware model, it will be understood that the clock-level description involves an amount of description less than that of the RTL description. This is advantageous in that the simulation can be performed at higher speed. However, a technique that uses a clock-level simulation to estimate the power consumption of a semiconductor device to be designed has not been known heretofore. Thus, there is much to be desired in the art.